`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   16:54:21 11/03/2011
// Design Name:   VGAController
// Module Name:   C:/Users/Tyson/Documents/Verilog Projects/CPU svn proj 3710/trunk/VGAControllerTEST.v
// Project Name:  CPU
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: VGAController
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module VGAControllerTEST;

	// Inputs
	reg clk;
	reg [9:0] objYStart;
	reg [9:0] objXStart;
	// Outputs
	wire vga_h_sync;
	wire vga_v_sync;
	wire vga_R;
	wire vga_G;
	wire vga_B;
	wire tmp, tmp2, invert, tmp3;
	// Instantiate the Unit Under Test (UUT)
	VGAController uut (
		.clk(clk), 
		.invert(invert),
		.pulse(tmp),
		.data(tmp2),
		.plyr_input(tmp3),
		.vga_h_sync(vga_h_sync), 
		.vga_v_sync(vga_v_sync), 
		.R(vga_R), 
		.G(vga_G), 
		.B(vga_B)
	);
	initial begin
		// Initialize Inputs
		clk = 0;


		// Wait 100 ns for global reset to finish
		#100;
   
		// Add stimulus here

	end
	
	always begin
	
	clk = ~clk;
	#10;
	end
      
endmodule

